Electronic circuits, such as integrated microcircuits, are used in a variety of products, from automobiles to microwaves to personal computers. Designing and fabricating microcircuit devices typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of microcircuit, its complexity, the design team, and the microcircuit fabricator or foundry that will manufacture the microcircuit. Typically, software and hardware “tools” verify the design at various stages of the design flow by running software simulators and/or hardware emulators, and errors in the design are corrected or the design is otherwise improved.
Several steps are common to most design flows. Initially, the specification for a new circuit is transformed into a logical design, sometimes referred to as a register transfer level (RTL) description of the circuit. With this logical design, the circuit is described in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. The logical design typically employs a Hardware Design Language (HDL), such as the Very high speed integrated circuit Hardware Design Language (VHDL). The logic of the circuit is then analyzed, to confirm that it will accurately perform the functions desired for the circuit. This analysis is sometimes referred to as “functional verification.”
After the accuracy of the logical design is confirmed, it is converted into a device design by synthesis software. The device design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. This device design generally corresponds to the level of representation displayed in conventional circuit diagrams. Preliminary timing estimates for portions of the circuit may be made at this stage, using an assumed characteristic speed for each device. In addition, the relationships between the electronic devices are analyzed, to confirm that the circuit described by the device design will correctly perform the desired functions. This analysis is sometimes referred to as “formal verification.”
Once the relationships between circuit devices have been established, the design is again transformed, this time into a physical design that describes specific geometric elements. This type of design often is referred to as a “layout” design. The geometric elements, which typically are polygons, define the shapes that will be created in various materials to manufacture the circuit. Typically, a designer will select groups of geometric elements representing circuit device components (e.g., contacts, gates, etc.) and place them in a design area. These groups of geometric elements may be custom designed, selected from a library of previously-created designs, or some combination of both. Lines are then routed between the geometric elements, which will form the wiring used to interconnect the electronic devices. Layout tools (often referred to as “place and route” tools), such as Mentor Graphics' IC Station or Cadence's Virtuoso, are commonly used for both of these tasks. After the design is finalized, the design can be used by fabricated to manufacturer the device.
There are many different fabrication processes for manufacturing a circuit, but most processes include a series of steps which deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and etch the exposed (or non-exposed) portions of the layer away. For example, a simple semiconductor circuit could be manufactured by the following steps. First, a positive type epitaxial layer is grown on a silicon substrate through chemical vapor deposition. Next, a nitride layer is deposited over the epitaxial layer. Then specific areas of the nitride layer are exposed to radiation, causing the exposed areas to be etched away, leaving behind exposed areas on the epitaxial layer, (i.e., areas no longer covered by the nitride layer). Specific shapes or patterns on these exposed areas then are subjected to a diffusion or ion implantation process. This causes dopants, (for example, phosphorus) to enter the exposed epitaxial layer and form negative wells. This process of depositing layers of material on the substrate or subsequent material layers, and then exposing specific patterns to radiation, dopants or other diffusion processes, is repeated a number of times. This series of steps allows the different physical layers of the circuit to be manufactured, forming gates, connecting layers, polysilicon layers, and eventually transistors on the substrate. The combination of these components make up what is often referred to as an integrated circuit device.
Each time that a layer is exposed to radiation or diffusion, a mask must be created to expose certain areas to the radiation or diffusion and protect the other areas from exposure. Each mask is created from circuit layout data. For each layer of material in the circuit that is masked and etched, corresponding layout design data must be used to create the mask. The geometric elements described in layout design data define the relative locations or areas of the circuit device that will be exposed to radiation or diffusion. A mask or reticle writing tool is used to create the mask or reticle based upon the layout design data, after which the mask can be used in a photolithographic process. This process of transferring the design from the mask to the substrate is often referred to as “printing” or “etching” the design.
As designers and manufacturers continue to increase the number of circuit components in a given area and/or shrink the size of circuit components, the shapes reproduced on the substrate (and thus the shapes in the mask) become smaller and closer together. This reduction in feature size increases the difficulty of faithfully reproducing the image intended by the layout design to the mask and onto the substrate. This difficulty often results in defects where the intended image is not accurately “printed” onto the substrate, creating flaws in the manufactured device. Accordingly, the terms “error” or “potential print error” are used herein to refer to a feature or group of features in layout design data that may not be accurately printed onto a substrate during a lithographic manufacturing process.
To address this problem, one or more resolution enhancement techniques are often employed. Examples of various resolution enhancement techniques are discussed in “Resolution Enhancement Technology: The Past, the Present, and Extensions for the Future,” Frank M. Schellenberg, Optical Microlithography XVII, edited by Bruce W. Smith, Proceedings of SPIE Vol. 5377, which article is incorporated entirely herein by reference. One of these techniques, radiation amplitude control, is often facilitated by modifying the layout design data employed to create the lithographic mask. One way to implement this technique, for example, is to adjust the edges of the geometric elements in the layout design so that the mask created from the modified layout data will control the radiation amplitude in a desired way during a lithographic process. The process of modifying the layout design data in this manner is often referred to as “optical proximity correction” or “optical process correction” (OPC).
As previously noted, a layout design is made up of a variety of geometric elements. In a conventional OPC process, the edges of the geometric elements (which are typically polygons) are fragmented, and the edge fragments are rearranged to reflect the desired modifications. For example, some OPC processes will reconfigure the edge fragments of a polygon to create serifs at one or more corners. The edge fragments are typically reconfigured according to one or more parameters, such as the size and spacing limitations on the edge fragments, or polygon placement. The values selected for these parameters have a significant impact on how and to what extent that the edge fragments within the layout data are modified during the OPC process. The set of parameter values used for an OPC process are often referred to as the “OPC recipe”.
Another way to implement the OPC technique involves adding geometric elements (sub-resolution assist features, or SRAFs) in the layout design. This approach is sometimes simply referred to as SRAF. While the conventional OPC approach certainly corrects many proximity effects, it does not address one proximity effect—variations in focus condition. The variations in focus condition become significant when an off-axis illumination scheme (one of the three major resolution enhancement technologies) is optimized for greatest depth of focus of densely placed features. SRAFs are designed to reduce the difference by making a relatively isolated main feature behave lithographically more like a densely-placed main feature. For example, scattering bars, a common type of SRAFs, may be placed adjacent to relatively isolated lines (main features), allowing the isolated lines to diffract light like dense lines. Here, a main feature is referred to as a feature that is intended to print.
An SRAF, as the name implies, is a sub-resolution feature that is not meant to print. It must be carefully adjusted in size and position so that it never prints over the needed process window. This determines the most important trade-off in SRAF generation and placement: making the assist features as large and dense as possible in order to create a more dense-like mask pattern, but not so large or dense that they print. Just like the conventional OPC approach, there are rule-based SRAF and model-based SRAF methods. The rule-based SRAF methods are quite common, but have difficulty with 2D placement. For example, there is a problem of what to do with contact or via features. The model-based SRAF methods show promise for complex 2D geometries, but are difficult to implement. The rule-based SRAF methods and the model-based SRAF methods can also be combined to take advantage of both the simplicity of the former and the high quality of the latter.
Once a layout design is finalized, it must be examined to ensure that the design does not have potential print errors (i.e., design features that may not be correctly printed during a lithograph process). If there are potential print errors, then these potential print errors must be corrected. For example, if the design includes only a few potential print errors, then a designer may either manually correct these errors. Alternately, a designer may employ an OPC process with a new recipe on the design to solve the problem. Some of these potential print errors may be due to missing or misplaced SRAFs. These errors should also be addressed during the repair process.
While performing OPC on layout design data can improve the fidelity of the lithographic process, OPC can be expensive in terms of both computing resources and processing time. Layout designs can be very large, and even one layout data file for a single layer of a field programmable gate array may be approximately 58 gigabytes. Accordingly, performing even a single OPC process on a design is computationally intensive. Repeating an OPC process to correct remaining potential print errors then only adds to time required to finalize the layout design. On the other hand, manually correcting potential print errors is very time consuming as well.